1. Technical Field
The present disclosure relates to the fabrication of spacers. More specifically, the present disclosure relates to fabricating spacers having vertical sidewalls and to improving spacer shape and spacer width.
2. Related Art
In integrated circuit fabrication technology, a spacer is a structural feature commonly formed proximate to a sidewall of a topographical feature. One function of the spacer may be to improve the electrical performance of a device comprising the topographical feature. Another function of the spacer is to act as a mask during fabrication.
For example, in modern complementary metal oxide semiconductor (CMOS) processes, oxide or nitride spacers may be formed at the sidewalls of a polycrystalline silicon (poly-Si) transistor gate in order to electrically isolate the gate from the transistor's source and drain terminals. Similarly, in modern bipolar junction transistor (BJT) technologies, in which the BJTs have self-aligned emitters, oxide spacers may be formed at an edge of a self-aligned emitter in order to isolate the emitter from the base electrode.
Further, spacers are used as ion implantation hard masks for achieving double-diffused structures in lightly doped drain/source metal oxide field-effect transistors (LDD-MOSFETs). Spacers may also be used as hard masks for transferring patterns in an underlying layer or substrate. In the latter application, the use of spacers enhances a conventional lithography process by allowing double the expected number of features to be transferred to the underlying layer or substrate in one exposure step. Furthermore, in self-aligned silicide layer formation, spacers may be used to prevent shorting the gate and source/drain terminals during the salicide process.
A spacer may also serve as an active terminal of a device. For example, in split-gate transistors, which are used in embedded charge trapping memory devices, a poly-Si spacer may be used to form one of the two gates of a split-gate transistor memory cell. The poly-Si spacer gate is typically metallized and serves as a select gate for the memory cell.
There are several parameters to consider when fabricating spacers, especially when they are to be used in the applications mentioned above. Etch rate, etch chemistry, material deposition thickness, among other parameters, may all affect the spacers' shape and width. Offsets in width or irregular sidewall profiles result from non-ideal fabrication conditions, which directly affect overall device performance.
For example, a split-gate transistor may have an undesired drive strength or selection threshold if there is an offset in the selection gate spacer's nominal width. Furthermore, a tapered or curved spacer sidewall profile may result in shorting the gate and drain terminals during a salicide process. Also, in applications where spacers are used for pattern transfer, incorrect feature sizes and incorrect pitch values may result from offsets in nominal spacer width and from tapered or curved spacer sidewall profiles.